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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 ________________ general description the max1245 12-bit data-acquisition system combines an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and ultra-low power consumption. it operates from a single +2.375v to +3.3v supply, and its analog inputs are software config- urable for unipolar/bipolar and single-ended/differential operation. the 4-wire serial interface directly connects to spi, qspi, and microwire devices without external logic. a serial strobe output allows direct connection to tms320-family digital signal processors. the max1245 works with an external reference, and uses either the internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions. this device provides a hard-wired shdn pin and a software-selectable power-down, and can be pro- grammed to automatically shut down at the end of a conversion. accessing the serial interface powers up the max1245, and the quick turn-on time allows it to be shut down between conversions. this technique can cut supply current to under 10? at reduced sampling rates. the max1245 is available in a 20-pin dip package and an ssop that occupies 30% less area than an 8-pin dip. for supply voltages from +2.7v to +5.25v, use the pin- compatible max147. ________________________applications portable data logging medical instruments battery-powered instruments data acquisition ____________________________features ? single +2.375v to +3.3v operation ? 8-channel single-ended or 4-channel differential analog inputs ? low power: 0.8ma (100ksps) 10? (1ksps) 1? (power-down mode) ? internal track/hold, 100khz sampling rate ? spi/qspi/microwire/tms320-compatible 4-wire serial interface ? software-configurable unipolar or bipolar inputs ? 20-pin dip/ssop packages max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 top view dip/ssop v dd sclk cs din sstrb dout dgnd agnd v dd vref shdn com ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max1245 ___________________pin configuration v dd i/o sck (sk)* mosi (so) miso (si) v ss shdn sstrb dout din sclk cs com agnd dgnd v dd ch7 0.1 m f 0.1 m f ch0 0v to +2.048v analog inputs max1245 cpu +2.5v vref +2.048v ___________t ypical operating circuit 19-1066; rev 0; 6/96 part ? max1245acpp max1245bcpp max1245acap 0? to +70? 0? to +70? 0? to +70? temp. range pin-package 20 plastic dip 20 plastic dip 20 ssop ________________or dering information ordering information continued at end of data sheet. ? contact factory for availability of alternate surface-mount packages. * contact factory for availability. max1245bcap 0? to +70? 20 ssop max1245bc/d 0? to +70? dice* inl (lsb) ?/2 ? ?/2 ? ? spi and qspi are registered trademarks of motorola, inc. microwire is a registered trademark of national semiconductor corp.
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.375v to +3.3v, com = 0v, f clk = 1.5mhz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps), vref = 2.048v applied to vref pin, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd .............................................. -0.3v to +6v agnd to dgnd.................................................... -0.3v to +0.3v ch0?h7, com to agnd, dgnd ............ -0.3v to (v dd + 0.3v) vref to agnd........................................... -0.3v to (v dd + 0.3v) digital inputs to dgnd............................................ -0.3v to +6v digital outputs to dgnd ........................... -0.3v to (v dd + 0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) plastic dip (derate 11.11mw/? above +70?) ......... 889mw ssop (derate 8.00mw/? above +70?) ................... 640mw cerdip (derate 11.11mw/? above +70?) .............. 889mw operating temperature ranges max1245_c_p ................................................... 0? to +70? max1245_e_p ................................................ -40? to +85? storage temperature range ............................ -60? to +150? lead temperature (soldering, 10sec) ............................ +300? 8 ? 35 65 t conv conversion time (note 5) 5.5 7.5 mhz 1.0 full-power bandwidth mhz 2.25 small-signal bandwidth db -85 channel-to-channel crosstalk db 76 sfdr spurious-free dynamic range db -76 thd total harmonic distortion db 68 sinad signal-to-noise + distortion ratio lsb ?.2 channel-to-channel offset matching ppm/? ?.25 gain temperature coefficient ?.5 bits 12 resolution lsb gain error (note 3) ?.5 ? lsb ?.0 inl relative accuracy (note 2) lsb ? dnl lsb ?.5 ? units min typ max symbol parameter external clock = 1.5mhz, 12 clocks/conversion internal clock, shdn = v dd internal clock, shdn = float max1245a -3db rolloff 50khz, 2v p-p (note 4) up to the 5th harmonic max1245b no missing codes over temperature conditions differential nonlinearity ns 40 aperture delay mhz 1.5 shdn = float ps <50 aperture jitter mhz 0.1 1.5 ? 2.0 t acq track/hold acquisition time external clock = 1.5mhz 0.225 internal clock frequency shdn = v dd 0 1.5 external clock frequency data transfer only dc accuracy (note 1) dynamic specifications (10khz sine-wave input, 0vp-p to 2.048vp-p, 100ksps, 1.5mhz external clock, bipolar input mode) conversion rate offset error
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc _______________________________________________________________________________________ 3 multiplexer leakage current pf 15 c in din, sclk, cs input capacitance ? ?.01 ? i in din, sclk, cs input leakage v 0.2 v hyst din, sclk, cs input hysteresis v 0.8 v inl din, sclk, cs input low voltage ? 0.01 10 shutdown vref input current k 18 25 vref input resistance ? 82 120 vref input current v 1.0 v dd + 50mv vref input voltage range (note 8) pf 16 input capacitance 0 to vref v ?ref/2 input voltage range, single- ended and differential (note 6) ? ?.01 ? units min typ max symbol parameter (note 7) v in = 0v or v dd unipolar, com = 0v vref = 2.048v bipolar, com = vref/2 on/off leakage current, v in = 0v or v dd (note 7) conditions v v dd /2 v dd /2 - 0.3 + 0.3 v im shdn input mid voltage ? ?.0 i in shdn input current v 0.4 v inl shdn input low voltage v v dd - 0.4 v inh shdn input high voltage shdn = 0v or v dd na ?0 shdn maximum allowed leakage, mid input v v dd /2 v flt shdn voltage, floating shdn = open shdn = open electrical characteristics (continued) (v dd = +2.375v to +3.3v, com = 0v, f clk = 1.5mhz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps), vref = 2.048v applied to vref pin, t a = t min to t max , unless otherwise noted.) mv ?.3 psr supply rejection (note 9) ma 0.8 1.3 i dd positive supply current ? ?.01 ?0 i l three-state leakage current v v dd - 0.375 v oh output voltage high v 0.5 v ol output voltage low 0.4 v 2.375 3.3 v dd positive supply voltage pf 15 c out three-state output capacitance v dd = 2.375v to 3.3v, full-scale input, external reference = 2.048v operating mode, full-scale input cs = v dd (note 7) cs = v dd i source =0.5ma i sink = 16ma i sink = 5ma 1.2 10 power-down v 2.0 v inh din, sclk, cs input high voltage analog/com inputs external reference digital inputs (din, sclk, cs , shdn ) digital outputs (dout, sstrb) power requirements ?
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 4 _______________________________________________________________________________________ timing characteristics (v dd = +2.375v to +3.3v, com = 0v, t a = t min to t max , unless otherwise noted.) note 1: tested at v dd = +2.375v; com = 0v; unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: external reference (vref = +2.048v), offset nulled. note 4: ground ?n?channel; sine wave applied to all ?ff?channels. note 5: conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: the common-mode range for the analog inputs is from agnd to v dd . note 7: guaranteed by design. not subject to production testing. note 8: adc performance is limited by the converter? noise floor, typically 300?p-p. note 9: measured as | v fs (2.375v) - v fs (3.3v) | . din to sclk setup ns 400 t str cs rise to sstrb output disable ns 240 t sdv cs fall to sstrb output enable 260 t sstrb sclk fall to sstrb ns 300 t cl sclk pulse width low ns 300 sclk pulse width high ns 0 cs to sclk rise hold ns 200 t css cs to sclk rise setup ns 400 t tr cs rise to output disable ns 240 t dv cs fall to output enable t do sclk fall to output data valid ns 0 t dh din to sclk hold ns ? 2.0 t acq acquisition time 0 t sck sstrb rise to sclk rise ns 200 t ds units min typ max symbol internal clock mode only (note 7) external clock mode only, figure 2 external clock mode only, figure 1 figure 1 figure 2 figure 1 conditions figure 1 ns 20 260 t csh t ch __________________________________________typical operating characteristics (v dd = 2.5v, vref = 2.048v, f clk = 1.5mhz, c load = 20pf, t a = +25?, unless otherwise noted.) ns 1.25 2.375 supply current vs. supply voltage 1.00 v dd (v) i dd (ma) 2.875 0.75 0.50 3.375 3.125 2.625 r l = code = 101010100000 max1245-01 c load = 50pf c load = 20pf 0.90 0.65 -55 -30 70 supply current vs. temperature 0.85 0.80 0.75 0.70 temperature (?) i dd (ma) 20 145 120 -5 45 95 max1245-02 r l = code = 101010100000 0.50 0.00 integral nonlinearity vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) inl (lsb) max1245-03 2.375 2.875 3.375 3.125 2.625 parameter
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc _______________________________________________________________________________________ 5 0.50 0 -55 -30 45 integral nonlinearity vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature (?c) inl (lsb) 20 -5 70 95 145 120 max1245-04 v dd = 2.375v 0.50 0 offset vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) offset (lsb) max1245-05 2.375 2.875 3.375 3.125 2.625 0.50 0 -55 -30 45 offset vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature (?c) offset (lsb) 20 -5 70 145 120 95 max1245-06 0.50 0 channel-to-channel offset matching vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) offset matching (lsb) max1245-07 2.375 2.875 3.375 3.125 2.625 0.50 0 -55 -30 20 gain error vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature (?c) gain error (lsb) -5 45 120 145 95 70 max1245-10 0.50 0 -55 -30 45 channel-to-channel offset matching vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature (?c) offset matching (lsb) 20 -5 70 145 120 95 max1245-08 0.50 0 gain error vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) gain error (lsb) max1245-09 2.375 2.875 3.375 3.125 2.625 0.50 0 channel-to-channel gain matching vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) gain matching (lsb) max1245-11 2.375 2.875 3.375 3.125 2.625 0.50 0 -55 -30 20 channel-to-channel gain matching vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature (?c) gain matching (lsb) -5 45 145 120 95 70 max1245-12 ____________________________typical operating characteristics (continued) (v dd = 2.5v, vref = 2.048v, f clk = 1.5mhz, c load = 20pf, t a = +25?, unless otherwise noted.)
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (v dd = 2.5v, vref = 2.048v, f clk = 1.5mhz, c load = 20pf, t a = +25?, unless otherwise noted.) 100 1000 0.1 0.1 average supply current vs. conversion rate 10 1 conversions per channel per second (hz) i dd (?) 10 1 1k 10k 100 100k max1245-13 v dd = v ref = 2.5v code = 101010100000 r l = 8 channels 1 channel 0.15 -0.25 0.25 0 4096 integral nonlinearity -0.20 0.20 0.10 -0.10 -0.15 inl (bits) 0.05 0 -0.05 2048 digital code 20 -120 0 fft plot -100 0 -80 -40 -20 -60 10 20 30 40 50 amplitude (db) frequency (khz) f tone = 10ksps f sample = 100ksps 12.0 10.5 10.0 1 10 100 effective number of bits vs. input frequency max1245-14 input frequency (khz) effective number of bits 11.5 11.0
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc _______________________________________________________________________________________ 7 name function 1? ch0?h7 sampling analog inputs 9 com ground reference for analog inputs. sets zero-code voltage in single-ended mode. must be stable to ?.5lsb. pin 10 shdn three-level shutdown input. pulling shdn low shuts the max1245 down to 10? (max) supply current; otherwise, the max1245 is fully operational. letting shdn float sets the internal clock frequency to 1.5mhz. pulling shdn high sets the internal clock frequency to 225khz. see hardware power-down section. 11 vref external reference voltage input for analog-to-digital conversion 15 dout serial data output. data is clocked out at the falling edge of sclk. high impedance when cs is high. 14 dgnd digital ground 13 agnd analog ground 12, 20 v dd positive supply voltage 19 sclk serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. (duty cycle must be 40% to 60%.) 18 cs active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout is high impedance. 17 din serial data input. data is clocked in at the rising edge of sclk. 16 sstrb serial strobe output. in internal clock mode, sstrb goes low when the max1245 begins the a/d con- version and goes high when the conversion is done. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high (external clock mode). ______________________________________________________________pin description v dd 6k dgnd dout c load 50pf c load 50pf dgnd 6k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol v dd 6k dgnd dout c load 50pf c load 50pf dgnd 6k dout a) v oh to high-z b) v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disable time
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 8 _______________________________________________________________________________________ _______________detailed description the max1245 analog-to-digital converter (adc) uses a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog sig- nal to a 12-bit digital output. a flexible serial interface provides easy interface to microprocessors (?s). no external hold capacitors are required. figure 3 is a block diagram of the max1245. pseudo-differential input the sampling architecture of the adc? analog compara- tor is illustrated in the equivalent input circuit (figure 4). in single-ended mode, in+ is internally switched to ch0?h7, and in- is switched to com. in differential mode, in+ and in- are selected from the following pairs: ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the channels with tables 2 and 3. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side (in-) must remain sta- ble within ?.5lsb (?.1lsb for best results) with respect to agnd during a conversion. to accomplish this, connect a 0.1? capacitor from in- (the selected analog input) to agnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acqui- sition interval spans three sclk cycles and ends on the falling sclk edge after the last bit of the input control word has been entered. at the end of the acquisition inter- val, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplexer switching c hold from the positive input, in+, to the negative input, in- (in single-ended mode, in- is simply com). this unbalances node zero at the input of the comparator. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equivalent to transferring a charge of 16pf x [(v in + ) - (v in -)] from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. track/hold the t/h enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single-ended inputs, in- is connected to com, and the converter samples the ??input. if the converter is set up for dif- ferential inputs, in- connects to the ??input, and the difference of | in+ - in- | is sampled. at the end of the conversion, the positive input connects back to in+, and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. it is calculated by: t acq = 9 x (r s + r in ) x 16pf input shift register control logic int clock output shift register t/h analog input mux 12-bit sar adc in dout sstrb v dd dgnd agnd sclk din ch0 ch1 ch3 ch2 ch7 ch6 ch5 ch4 com vref out ref clock 1 2 3 4 5 6 7 8 10 11 9 15 16 17 18 19 max1245 cs shdn 12, 20 14 13 figure 3. block diagram ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com c switch track t/h switch r in 12k c hold hold 12-bit capacitive dac vref zero comparator + 16pf single-ended mode: in+ = cho?h7, in- = com. differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 4. equivalent input circuit
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc _______________________________________________________________________________________ 9 0.1? 2.048v v dd dgnd agnd com cs sclk din dout sstrb shdn +2.5v n.c. 0.01? ch7 vref c1 0.1 m f 0v to 2.048v analog input oscilloscope ch1 ch2 ch3 ch4 * full-scale analog input, conversion result = $fff (hex) max1245 +2.5v 1.5mhz oscillator sclk sstrb dout* figure 5. quick-look circuit where r in = 12k , r s = the source impedance of the input signal, and t acq is never less than 2.0?. note that source impedances below 1k do not significantly affect the ac performance of the adc. higher source impedances can be used if an input capacitor is con- nected to the analog inputs, as shown in figure 5. note that the input capacitor forms an rc filter with the input source impedance, limiting the adc? signal bandwidth. input bandwidth the adc? input tracking circuitry has a 2.25mhz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic sig- nals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input protection internal protection diodes, which clamp the analog input to v dd and agnd, allow the channel input pins to swing from agnd - 0.3v to v dd + 0.3v without dam- age. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than agnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off channels over two milliamperes, as excessive current will degrade the conversion accuracy of the on channel. quick look to quickly evaluate the max1245? analog perfor- mance, use the circuit of figure 5. the max1245 requires a control byte to be written to din before each conversion. tying din to v dd feeds in control bytes of $ff (hex), which trigger single-ended unipolar conver- sions on ch7 in external clock mode without powering down between conversions. in external clock mode, the sstrb output pulses high for one clock period before the most significant bit of the 12-bit conversion result is shifted out of dout. varying the analog input to ch7 alters the sequence of bits from dout. a total of 15 clock cycles is required per conversion. all transitions of the sstrb and dout outputs occur on the falling edge of sclk. how to start a conversion a conversion is started by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the max1245? internal shift register. after cs falls, the first arriving logic ??bit defines the msb of the control byte. until this first ?tart?bit arrives, any number of logic ??bits can be clocked into din with no effect. table 1 shows the control-byte format. the max1245 is compatible with microwire, spi, and qspi devices. for spi, select the correct clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating circuit, the simplest soft- ware interface requires only three 8-bit transfers to
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 10 ______________________________________________________________________________________ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 bit name description 7(msb) start the first logic ??bit after cs goes low defines the beginning of the control byte. 6 sel2 these three bits select which of the eight channels are used for the conversion (tables 2 and 3). 5 sel1 4 sel0 3 uni/bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0v to vref can be converted; in bipolar mode, the signal can range from -vref/2 to +vref/2. 2 sgl/dif 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to com. in differential mode, the voltage difference between two channels is measured (tables 2 and 3). 1 pd1 selects clock and power-down modes. 0(lsb) pd0 pd1 pd0 mode 0 0 power-down (i q = 1.2?) 0 1 unassigned 1 0 internal clock mode 1 1 external clock mode table 1. control-byte format sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 00 0 + 10 0 + 00 1 + 10 1 + 01 0 + 11 0 + 01 1 + 11 1 + table 2. channel selection in single-ended mode (sgl/ dif = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 00 0 + 00 1 + 01 0 + 01 1 + 10 0 + 10 1 + 11 0 + 11 1 ? table 3. channel selection in differential mode (sgl/ dif = 0)
perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the 12-bit conversion result). see figure 17 for max1245 qspi connections. simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 100khz to 1.5mhz. 1) set up the control byte for external clock mode and call it tb1. tb1 should be of the format: 1xxxxx11 binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and, simultaneously, receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb3. 6) pull cs high. figure 6 shows the timing for this sequence. bytes rb2 and rb3 will contain the result of the conversion padded with one leading zero and three trailing zeros. the total conversion time is a function of the serial clock frequency and the amount of idle time between 8-bit transfers. make sure that the total conversion time does not exceed 120?, to avoid excessive t/h droop. digital output in unipolar input mode, the output is straight binary (figure 14). for bipolar inputs, the output is two?-com- plement (figure 15). data is clocked out at the falling edge of sclk in msb-first format. clock modes the max1245 may use either an external serial clock or the internal clock to perform the successive-approxima- tion conversion. in both clock modes, the external clock shifts data in and out of the max1245. the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 7?0 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital con- version. sstrb pulses high for one clock period after the control byte? last bit. successive-approximation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (figure 6). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 8 shows the sstrb timing in external clock mode. the conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the serial clock frequency is less than 100khz, or if serial-clock interruptions could cause the conversion interval to exceed 120?. max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ______________________________________________________________________________________ 11 sstrb cs sclk din dout 14 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb acquisition (sclk = 1.5mhz) idle filled with zeros idle conversion t acq a/d state rb1 rb2 rb3 2.0? figure 6. 24-clock external-clock-mode conversion timing (microwire and spi compatible, qspi compatible with f clk 1.5mhz)
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 12 ______________________________________________________________________________________ internal clock in internal clock mode, the max1245 generates its own conversion clock internally. this frees the ? from the burden of running the sar conversion clock and allows the conversion results to be read back at the proces- sor? convenience, at any clock rate from zero to 1.5mhz. sstrb goes low at the start of the conversion and then goes high when the conversion is complete. sstrb will be low for a maximum of 7.5? ( shdn = float), during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out of this register at any time after the conversion is complete. after sstrb goes high, the next falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first format (figure 9). cs does not need to be held low once a conversion is started. pulling cs high prevents data from being clocked into the max1245 and three-states dout, but it does not adversely affect an internal clock-mode conversion already in progress. when internal clock mode is t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb figure 8. external-clock-mode sstrb detailed timing cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 7. detailed serial-interface timing
selected, sstrb does not go into a high-impedance state when cs goes high. figure 10 shows the sstrb timing in internal clock mode. in this mode, data can be shifted in and out of the max1245 at clock rates exceeding 1.5mhz, provid- ed that the minimum acquisition time, t acq , is kept above 2.0?. data framing the falling edge of cs does not start a conversion on the max1245. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conversion starts on the falling edge of sclk, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any time the converter is idle; e.g., after v dd is applied. or the first high bit clocked into din after bit 5 of a con- version in progress is clocked onto the dout pin. if cs is toggled before the current conversion is com- plete, then the next high bit clocked into din is recog- nized as a start bit; the current conversion is terminated, and a new one is started. max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ______________________________________________________________________________________ 13 sstrb cs sclk din dout 14 8 12 18 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b11 msb b10 b9 b2 b1 b0 lsb filled with zeros idle conversion 7.5? max (shdn = float) 2 3 5 6 7 9 10 11 19 21 22 23 t conv acquisition (sclk = 1.5mhz) idle a/d state 2.0? pd0 clock in t sstrb t csh t conv t sck sstrb sclk dout t css t do note: for best noise performance, keep sclk low during conversion. cs figure 9. internal clock mode timing figure 10. internal clock mode sstrb detailed timing
the fastest the max1245 can run is 15 clocks per conver- sion with cs held low between conversions. figure 11a shows the serial-interface timing necessary to perform a conversion every 15 sclk cycles in external clock mode. if cs is low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. most microcontrollers require that conversions occur in multiples of eight sclk clocks; 16 clocks per conversion will typically be the fastest that a microcontroller can drive the max1245. figure 11b shows the serial-inter- face timing necessary to perform a conversion every 16 sclk cycles in external clock mode. __________ applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates the max1245 in internal clock mode, ready to convert with sstrb = high. after the power supplies have stabi- lized, the internal reset time is 10?, and no conver- sions should be performed during this phase. sstrb is high on power-up and, if cs is low, the first logical 1 on din will be interpreted as a start bit. until a conversion takes place, dout shifts out zeros. power-down the max1245? automatic power-down mode can save considerable power when operating at speeds below the maximum sampling rate. figure 13 shows the aver- age supply current as a function of the sampling rate. you can save power by placing the converter in a low- current shutdown state between conversions. select power-down via bits 1 and 0 of the din control byte with shdn high (tables 1 and 4). pull shdn low at any time to shut down the converter completely. shdn overrides bits 1 and 0 of the control byte (table 5). power-down mode turns off all chip functions that draw quiescent current, reducing i dd typically to 1.2?. figures 12a and 12b illustrate the various power-down sequences in both external and internal clock modes. software power-down software power-down is activated using bits pd1 and pd0 of the control byte. as shown in table 4, pd1 and pd0 max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 14 ______________________________________________________________________________________ sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 conversion result 1 sstrb b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control byte 2 s 1 8181 cs sclk din dout s control byte 0 control byte 1 s conversion result 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 conversion result 1 figure 11a. external clock mode, 15 clocks/conversion timing figure 11b. external clock mode, 16 clocks/conversion timing
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ______________________________________________________________________________________ 15 powered up hardware power- down powered up powered up 12 data bits 12 data bits invalid data valid data external external sx xxxx 11 s 00 xx x x x xx xxx s11 software power-down mode dout din clock mode shdn sets external clock mode sets external clock mode sets software power-down software power-down powered up powered up data valid data valid internal sx xxxx 10 s 00 xx x x x s mode dout din clock mode sets internal clock mode sets power-down conversion conversion sstrb figure 12a. timing diagram power-down modes, external clock figure 12b. timing diagram power-down modes, internal clock pd1 pd0 device mode 1 1 external clock 1 0 internal clock 0 1 unassigned 0 0 power-down shdn device internal clock state mode frequency 1 enabled 225khz floating enabled 1.5mhz 0 power-down n/a table 4. software power-down and clock mode table 5. hard-wired power-down and internal clock frequency
also specify the clock mode. when software shutdown is asserted, the adc continues to operate in the last speci- fied clock mode until the conversion is complete. then the adc powers down into a low quiescent-current state. in internal clock mode, the interface remains active and con- version results can be clocked out after the max1245 has entered a software power-down. the first logical 1 on din is interpreted as a start bit, and powers up the max1245. following the start bit, the data input word or control byte also determines clock mode and power-down states. for example, if the din word contains pd1 = 1, the chip remains powered up. if pd0 = pd1 = 0, a power-down resumes after one conversion. hardware power-down pulling shdn low places the converter in hardware power-down. unlike the software power-down mode, the conversion is not completed; it stops coincidentally with shdn being brought low. shdn also controls the clock frequency in internal clock mode. letting shdn float sets the internal clock frequency to 1.5mhz. when returning to normal operation with shdn floating, there is a t rc delay of approximately 2m x c l , where c l is the capacitive loading on the shdn pin. pulling shdn high sets the internal clock frequency to 225khz. this feature eases the settling-time requirement for the reference voltage. external reference an external reference is required for the max1245. the reference voltage range is 1v to v dd . at vref, the input impedance is a minimum of 18k for dc currents. during a conversion, the reference must be able to deliver up to 250? dc load current and have an output impedance of 10 or less. if the refer- ence has higher output impedance or is noisy, bypass it close to the vref pin with a 0.1? capacitor. transfer function table 6 shows the full-scale voltage ranges for unipolar and bipolar modes using a 2.048v reference. the external reference must have a temperature coefficient of 4ppm/? or less to achieve accuracy to within 1lsb over the commercial temperature range of 0c to +70?. figure 14 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 15 shows the bipolar input/output transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1lsb = 500? (2.048v / 4096) for unipolar operation and 1lsb = 500? [(2.048v / 2 - -2.048v / 2) / 4096] for bipolar operation. layout, grounding, and bypassing for best performance, use printed circuit boards. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 16 shows the recommended system ground connections. a single-point analog ground (?tar ground point) should be established at agnd, sepa- rate from the logic ground. connect all other analog grounds and dgnd to the star ground. no other digital system ground should be connected to this ground. the ground return to the power supply for the star max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 16 ______________________________________________________________________________________ 100 1000 0.1 0.1 average supply current vs. conversion rate 10 1 conversions per channel per second (hz) i dd (?) 10 1 1k 10k 100 100k max1245-13 1 channel 8 channels v dd = v ref = 2.5v code = 101010100000 r l = figure 13. average supply current vs. conversion rate table 6. full scale and zero scale unipolar mode bipolar mode full scale zero scale positive zero negative full scale scale full scale vref + com com vref/2 com -vref/2 + com + com
ground should be low impedance and as short as pos- sible for noise-free operation. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypass the supply to the star ground with 0.1? and 4.7? capacitors close to pin 20 of the max1245. minimize capacitor lead lengths for best supply-noise rejection. if the +2.5v power supply is very noisy, a 10 resistor can be connected as a lowpass filter (figure 16). max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ______________________________________________________________________________________ 17 output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 (com) fs fs - 3/2lsb fs = vref + com zs = com input voltage (lsbs) 1lsb = vref 4096 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com input voltage (lsbs) output code zs = com +fs - 1lsb ( vref/2) + com fs = vref 2 -fs = + com -vref 2 1lsb = vref 4096 figure 14. unipolar transfer function, full scale (fs) = vref + com, zero scale (zs) = com figure 15. bipolar transfer function, full scale (fs) = vref / 2 + com, zero scale (zs) = com +2.5v +2.5v gnd supplies dgnd +2.5v dgnd com agnd v dd digital circuitry max1245 r* = 10 w * optional figure 16. power-supply grounding connection
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc 18 ______________________________________________________________________________________ 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 max1245 mc683xx ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com shdn v dd sclk cs din sstrb dout dgnd agnd v dd vref (power supplies) sck pcs0 mosi miso clock connections not shown 0.1 m f 4.7 m f (gnd) 0.1 m f analog inputs +3v +2.5v +2.048v figure 17. max1245 qspi connections high-speed digital interfacing with qspi the max1245 can interface with qspi using the circuit in figure 17 (f sclk = 1.5mhz, cpol = 0, cpha = 0). this qspi circuit can be programmed to do a conversion on each of the eight channels. the result is stored in memory without taxing the cpu, since qspi incorporates its own micro-sequencer. because the maximum external clock frequency is 1.5mhz, the max1245 is qspi compatible up to 1.5mhz.
max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ______________________________________________________________________________________ 19 tms320lc3x-to-max1245 interface figure 18 shows an application circuit to interface the max1245 to the tms320 in external clock mode. the tim- ing diagram for this interface circuit is shown in figure 19. use the following steps to initiate a conversion in the max1245 and to read the results: 1) the tms320 should be configured with clkx (transmit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. clkx and clkr on the tms320 are tied together with the max1245? sclk input. 2) the max1245? cs pin is driven low by the tms320? xf_ i/o port, to enable data to be clocked into the max1245? din. 3) an 8-bit word (1xxxxx11) should be written to the max1245 to initiate a conversion and place the device into external clock mode. refer to table 1 to select the proper xxxxx bit values for your specific application. 4) the max1245? sstrb output is monitored via the tms320? fsr input. a falling edge on the sstrb output indicates that the conversion is in progress and data is ready to be received from the max1245. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits rep- resent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) pull cs high to disable the max1245 until the next conversion is initiated. cs sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb b10 b1 lsb high impedance high impedance figure 19. tms320 serial-interface timing diagram xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320lc3x max1245 figure 18. max1245-to-tms320 serial interface
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1996 maxim integrated products printed usa is a registered trademark of maxim integrated products. max1245 +2.375v, low-power, 8-channel, serial 12-bit adc ________________________________________________________package information ___________________chip information transistor count: 2554 __ordering information (continued) ? contact factory for availability of alternate surface-mount packages. l dim a a1 b c d e e h l a dim d d d d d min 0.068 0.002 0.010 0.004 0.205 0.301 0.025 0? min 0.239 0.239 0.278 0.317 0.397 max 0.078 0.008 0.015 0.008 0.209 0.311 0.037 8? max 0.249 0.249 0.289 0.328 0.407 min 1.73 0.05 0.25 0.09 5.20 7.65 0.63 0? min 6.07 6.07 7.07 8.07 10.07 max 1.99 0.21 0.38 0.20 5.38 7.90 0.95 8? pins 14 16 20 24 28 max 6.33 6.33 7.33 8.33 10.33 inches inches millimeters millimeters a ssop shrink small-outline package h e d a a1 c b 0.65 bsc 0.0256 bsc 21-0056a e see variations ? 20 ssop -40? to +85? max1245beap ?/2 20 ssop -40? to +85? max1245aeap ? 20 plastic dip -40? to +85? max1245bepp ?/2 20 plastic dip -40? to +85? max1245aepp inl (lsb) pin-package temp. range part ?

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